This application incorporates by reference an application for Method For Protecting An Over-erasure Of Redundant Memory Cells During Test For High-density Nonvolatile Memory Semiconductor Devices earlier filed in Korean Industrial Property Office on the Dec. 31, 1997 and there duly assigned Ser. No. 97-81001.
The invention relates to nonvolatile semiconductor memory devices, and more particularly to a method for preventing over-erasure of redundant memory cells of nonvolatile semiconductor memories during test thereof.
Flash memories perform data access operations, i.e., reading and writing (or programming) at high speed as compared to other kinds of nonvolatile memories such as electrically erasable and programmable read only memories. Because of its high speed operation, flash memory has been adapted to portable computing devices, cellular phones, digital still cameras, and so on.
Typical construction of a flash memory cell (or cell transistor) appropriate for either single-bit or multi-bit storage is shown in FIG. 1. Source 3 and drain 4, each being formed of an N+ diffused region in a P+ semiconductor substrate or bulk 2, are separated from each other by a channel region (not numbered) in bulk 2. Floating gate 6 is formed over the channel region, and separated from it by a thin (e.g., less than 100 xc3x85 thick) insulating film 7. A second insulating film 9, such as an Oxe2x80x94Nxe2x80x94O (Oxide-Nitride-Oxide) film, is formed on floating gate 6 to isolate control gate 8 from floating gate 6. Source 3, drain 4, control gate 8, and bulk 2 are each connected to their corresponding voltage sources Vs (source voltage), Vd (drain voltage), Vg (gate voltage) and Vb (bulk voltage), for programming, erasing, and reading operations.
A selected memory cell is programmed by means of hot electron injection between its channel region and its floating gate. During a programming operation, source and bulk are held at a ground voltage, a high voltage (e.g., 10V) is applied to a control gate, and a hot electron injection voltage (e.g., 5-6V) is provided to drain. After programming, a selected memory cell has an increased threshold voltage (e.g., to 6-7V) due to the deposition of electrons in the floating gate, as shown in FIG. 2.
To read data from the programmed cell, a voltage of about 1V is applied to the drain, a power source voltage (e.g., about 4.5V) is applied to the control gate, and the source is held at the ground voltage. Since the increased threshold voltage of a programmed memory cell acts as a blocking potential against the gate voltage during a read-out operation, a programmed cell remains off during the read operation, while an erased cell turns on.
A memory cell is erased either by inducing F-N (Fowler-Nordheim) tunneling between its control gate and its source (hereinafter, this manner is referred to as a xe2x80x9csource erasingxe2x80x9d) or by inducing F-N tunneling between its control gate and its bulk (hereinafter, this manner is referred to as a xe2x80x9cbulk erasingxe2x80x9d).
In erase operations for most state-of-the-art flash memories, source regions (for source erasing) or bulk regions (for bulk erasing) of multiple memory cells are combined commonly, so that the memory cells can be spontaneously erased at the same time. The units of erasing (hereinafter referred to as a xe2x80x9csectorxe2x80x9d, for instance, one sector of, e.g., 16, 32, or 64 Kbytes) are determined in accordance with the number of separate source or bulk regions.
During such an erase operation of a memory cell, the control gate is coupled to a high negative voltage of about xe2x88x9210V, and source (for source erasing) or bulk (for source erasing) is held at a positive voltage of about 5V in order to induce tunneling therebetween. At the same time, drain and bulk (for source erasing), or drain and source (for bulk erasing) are conditioned at a high impedance state (or a floating state). Under these voltage bias conditions, a strong electric field is induced between the control gate and either the source or the bulk, and the electric field causes electrons to move from the floating gate into the source or the bulk. F-N tunneling normally occurs when an electric field in the range of 6-7 MV/cm is developed in the thin insulating film separating the floating gate and the source or bulk. An erased cell has a lower threshold voltage (e.g., 1-3V) than a programmed cell (e.g., 6-7 V), as shown in FIG. 2, and is thereby sensed as an on-cell.
Generally, since source erasing creates a smaller coupling capacitance between channel and floating gate than bulk erasing does, the source erasing brings about fewer over-erased cells. The source erasing, however, not only consumes larger power than the bulk erasing but also causes faster deterioration of tunnel oxide, on account of band-to-band tunneling current and a larger number of hot electrons in sources. In addition, a cell in a source erasing architecture occupies a larger area than a cell in a bulk erasing architecture because the cell for source erasing needs an additional N-region for its source. Furthermore, as a cell for the source erasing has an F-N tunneling area smaller than the bulk erasing with advancement of cell scaling-down, the source erasing may have a drawback of causing a decrease in the uniformity of threshold voltage distribution. Accordingly, the bulk erasing architecture is suitable for high-density devices, rather than the source erasing architecture.
Meanwhile, a cell array of a flash memory device is typically divided into a main field for storing data and a redundant field for repairing defects in the main field. The redundant field contains multiple spare memory cells arranged to repair defective cells of the main field due to hard defects or soft defects. The spare cells are substituted for the defective memory cells, so that a defective device can develop into a non-defective one as a whole. A usual manner for repairing cell defects is determined by the architecture of the core region (typically, defect repair uses row redundancy or column redundancy).
After wafer manufacturing processes, a flash memory device requires a test procedure (including programming, program-verifying, erasing, and erase-verifying operations) to identify whether the device has defects. During such a test, a flash memory device is tested by programming main-field cells, in sequence, and then erasing them by applying negative voltages to their word lines. And, such programming and erasing cycles for device test are performed repeatedly.
With repetitive erasing for device test, one or more cells may be erased below a minimum acceptable threshold voltage (e.g., 1V), as shown in FIG. 2. A cell erased below the minimum threshold is commonly referred to as being xe2x80x9cover-erasedxe2x80x9d. An over-erased cell acts xe2x80x9cdepletion-likexe2x80x9d and induces a leakage current on its associated bit-line, thereby causing errors when other cells on the same bit-line are read.
Accordingly, over-erased cells need erasure correction to raise their thresholds by about 1V. One solution for this is to perform an iterative process utilizing over-erase verification and low-voltage level programming.
For instance, an operation for curing over-erase cells of a flash memory device with a column redundant architecture, during such a device test, can begin with selecting a row (i.e., a word-line) and examining cells on the selected row one by one along columns (i.e., bit-lines) to determine whether there are over-erased cells. This procedure is commonly referred to as over-erase verification. In this verify operation, a cell is identified as over-erased when it conducts current in excess of the current expected at the lowest threshold voltage (e.g., 1V). Once a cell is identified as over-erased, it is programmed with low-level curing voltages (e.g., 2-5 V to the control gate, 6-9 V to the drain, and 0 V to the source and bulk). Curing the remaining cells on other rows is performed in the same fashion.
When some main-field cells within a sector become over-erased with repetitive erasing for device test, then redundant-field cells of the sector may also become over-erased because sources (for source erasing) or bulks (for bulk erasing) of the main- and redundant-field cells of the sector are connected to a common voltage (e.g., 5V). In this case, however, it may not be possible to cure the over-erased redundant-field cells because of the conventional redundancy scheme, in which the redundant-field cells cannot be addressed until they are substituted for the failed main-field cells by means of, for example, a laser fusing or electrical fusing technique. When redundant-field cells are too much over-erased without any correction, they will be unavailable for repairing failed cells of the main field. Nevertheless, the redundant field over-erasure correction is not presently at issue in the art because almost all of conventional flash memories adopt source erasing scheme that causes relatively small extent of cell over-erasure, or because the cells of the memories are large enough not to consider over-erasure problem of the redundant field. And furthermore, the bulk erasing architecture may be essential for increasing flash memory capacity, notwithstanding its over-erasure flaw.
Based on the above and foregoing, it can be appreciated that the over-erasure of redundant field cannot be overlooked any longer upon designing advanced higher-density devices; since the number of factors to affect cell characteristics increases with the decrease in cell size, the number of erasing operations to check defective cells will increase more and more with device density, so that the redundant field over-erasure problem will turn more serious in view of device production yields.
The present invention is intended to solve the problems described above. And, it is an object of the invention to provide a method for preventing a redundant field from being over-erased when the redundant field is erased together with a main field during device test before repair of failed cells.
According to an aspect of the present invention, a method for protecting against over-erasure in a nonvolatile memory device with bulk erasing architecture is provided, which includes programming memory cells included in a redundant field of a selected memory cell sector, and testing the memory device for repair of failed cells in a main field of the sector by erasing memory cells included in the main field.
According to another aspect of the invention, a method for testing a nonvolatile memory device before repair of failed cells in the memory device is disclosed, which includes erasing memory cells included in a main field and a redundant field of a selected sector, and correcting over-erased memory cells included in the main and redundant fields of the selected sector.
According to yet another aspect of the invention, a method of testing a nonvolatile memory device prior to repair of failed cells is provided, that includes the steps of programming memory cells included in the main and redundant fields of a sector, erasing the memory cells included in the main and redundant fields, and programming over-erased cells of the memory cells included in the main and redundant fields.
In a more specific embodiment, the method includes the steps of programming memory cells included in the main and redundant fields, applying a predetermined negative voltage to the word lines of the main field and the redundant field and applying a predetermined voltage to bulk regions of the main and redundant fields, detecting over-erased memory cells in the main and redundant fields, and programming the over-erased memory cells included in the main field and the redundant field.
According to yet another aspect of the invention, a nonvolatile memory device is provided that comprises a plurality of sectors each of which includes a main field of memory cells and a redundant field of memory cells, an over-erase detection circuit which detects over-erased memory cells in both a main field and a redundant field of a sector during device test before repair of failed cells in the memory device, and an over-erase correction circuit which performs over-erasure correction for the detected over-erased cells in both the main and redundant fields before the repair of the failed memory cells.
In an embodiment, the memory device comprises an address generator for generating addresses to program the memory cells in both the main and redundant fields before repair of failed memory cells in the main and redundant fields, a flag generator for generating flag signals in response to the addresses, and a data path selector for providing selective connections between a plurality of data input/output lines and the memory cells in the main and redundant fields in response to the flag signals.